Comparative study on Wordlength Reduction and Truncation for low power multipliers

Power consumption in Digital Signal Processing systems directly relies on the precision of multipliers. As bigger bitwidths are desirable for achieving higher precisions, they result in bigger multipliers with high toggling profiles and higher power figures. In recent years some techniques that trade power for accuracy by removing or reconfiguring blocks of the multiplier have been made available. Choosing the correct technique and implementing it can make a big difference regarding power. This being specially important on low-power battery-operated devices, where a longer life could be preferred to a higher output precision. Operand Reduction and Truncated multipliers are two such techniques. They are reviewed in this paper and their effectiveness and power vs accuracy exchange profiles are compared and analyzed for ASIC design via simulation. Comparative results are presented after applying both techniques to a 16-bit Wallace tree-based multiplier synthesized in 90 nm low power standard cells.