A 200 MHz register-based wave-pipelined 64 M synchronous DRAM

A new register-based wave-pipelined scheme for synchronous DRAMs (SDRAMs) is proposed. In this scheme, (N-1) registers are located between a read data bus line pair and a data output buffer and (N-1) read data are stored in parallel in these registers, where N denotes the CAS latency. Since the column data path is not divided and the read data is transmitted directly to the registers, the burst read operation can easily be achieved at a higher operation frequency without a large area penalty or degradation of an internal timing margin. Measured results show that the 64 M SDRAM based on the register-based wave-pipelined scheme can operate up to 200 MHz.