The pipeline analysis of the complex algorithms adopted in the DSP based image processing

Algorithm optimization is an important part of DSP real-time system. In image processing, many core algorithms are the image traversal manipulation. Because there are a large number of multi-loop and generally loop is the best opportunity to improve the algorithm efficiency, those core algorithms efficiency can be improved greatly if the high effective software pipeline can be implemented. C6000 is a kind of chip with very long instruction word (VLIW) architecture, which can execute up to eight instructions in parallel. Adopting this parallelism is central to achieving peak performance. Instruction parallelism in C/C++ code is a kind of software pipelining to the loops. In software pipelining, multiple iterations of a loop are executed simultaneously in software[1][2]. In this paper, based on the actual code used in the real project, an algorithm to analysis algorithm complexity and run effectively in DSP is presented, so a significant increase in speed of the real-time image processing is possible.