A selectively deposited poly-gate ITLDD process with self-aligned LDD/channel implantation

An inverse-T lightly doped drain (ITLDD) CMOS process which features improved hot-carrier effects and self-aligned source/drain and channel implantation profiles is presented. Compensation effects by the heavy channel doping on the light N/sup -//P/sup -/ profile are minimized in this ITLDD structure, because the implants are self-aligned to the polysilicon-gate edge. In addition, because selective polysilicon deposition rather than an incomplete poly-gate etchback is used to define the ITLDD structure, a simpler, more manufacturable process is obtained due to improved control of the thin poly-gate shelf thickness.<
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