Fuzzy/scalar RISC processor: architectural level design and modeling

This paper presents the design and modeling issues of the fuzzy/scalar processor which is intended to perform standard scalar operations, as well as specialized fuzzy logic operations at very high speed. The reduced instruction set (RISC) architecture was chosen for the processor implementation. This high performance and, at the same time, extremely flexible device, can be used in a variety of applications where high speed standard and/or fuzzy logic operations are required. The high-level simulation results of the fuzzy/scalar reduced instruction set processor model (codename F/S RISC), are presented. The model built with Mentor Graphics "M" language was simulated using Lsim simulator at the clock frequency of 100 MHz. The current technology for the implementation of F/S RISC processor is chosen to be 1.2 /spl mu/m n-well CMOS.