Sub-0.25 /spl mu/m ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications

Fully-depleted (FD) 0.2 /spl mu/m SOI CMOS devices have been fabricated with a single N+ gate process. As an ultra-thin film is required to optimize fully-depleted 0.2 /spl mu/m SOI devices, a recessed channel structure has been used in order to prevent any contact problems. Dynamic performance has been demonstrated down to 1 V supply voltage with 0.25 /spl mu/m ring oscillators (propagation delay of 80 ps at 1.5 V) and 0.2 /spl mu/m 16 K SRAM (access time of 6 ns at 1.5 V). These results show that 0.2 /spl mu/m FD SOI devices meet the requirements for low voltage and low power applications.