Low power design of two-dimensional DCT

This paper discusses several techniques used in reducing power for a two-dimensional discrete cosine transform (2D DCT) design. These techniques include removal of circuit blocks that computes the DCT coefficients which will be quantized to zeros, re-ordering of operations in constant-multipliers to reduce transition probability, and re-designing cells for low-voltage operation. An 8/spl times/8 2D DCT built with two 1D DCT employing these techniques is designed. The estimated power consumption for this 8/spl times/8 2D DCT is 16.95 mW.