Low-power digital PLL with one cycle frequency lock-in time for clock syntheses up to 100 MHz using 32,768 Hz reference clock

A low-power Digital Phase Locked Loop (DPLL) with +/- 100 ps jitter, and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a reference frequency of 32,768 Hz, for advanced power management both at a device level and at a system level.