A closed-form solution to the damped RLC circuit with applications to CMOS ground bounce estimation

A simplified RLC model depicting a packaged CMOS device is used to determine the fall time of an output buffer. The fall time is dependent on how many outputs are switching simultaneously. The analysis was compared with the measurements of a 0.5 /spl mu/m CMOS test chip with good results. These results indicate that the fall time of a buffer is determined by the parasitic components in the system (R, L and C) and may not be the same as the intrinsic fall time of the output buffer in an ideal environment, i.e., L=0.