Performance evaluation of input buffered ATM switch architectures: throughout, delay and packet loss analyses

A copy network followed by a point-to-point switching network is a design approach that has been traditionally used for implementing asynchronous transfer mode (ATM) multicast architectures. An inherent limitation in the design of the copy network is the overflow, and a possible solution to this problem is to store the packets in a buffer for a later delivery by means of a shared-memory input buffering architecture. We investigate the performance of this buffering scheme with regard to throughput, average packet delay, and packet loss probability.