Design of A 10Gb/s in-line scalable Network Security Processor array

Design of a Gigabit In-Line scalable Network Security Processor on one chip is presented. With 8 parallel chips array and some control logic, the design may be used in 10 Gigabit Ethernet. Moreover, custom-specific off-chip crypto algorithms can replace the standard one on the chip through pr-reserved data interface, which improves the scalability of the design in crypto operation.