A one gigaFLIPS fuzzy logic control chip using only combinational logic and Field Programmable Gate Arrays

A real-time fully parallelized fuzzy logic control chip has been designed and implemented in a Xillinx Spartan IIe Field Programmable Gate Array. The current design handles two inputs and one output. Five membership functions are used to fuzzify each input signal, and five membership functions are used to defuzzify the output. Mamdani fuzzy inference is used to evaluate the 25 rules in the rule matrix. Two defuzzification schemes, weighted average and Hemmelman's average have been implemented and evaluated. Fuzzification, rule evaluation, and defuzzification are all performed in a parallel architecture that utilizes only combinational logic. Testing indicates a worst case delay of approximately 25 ns, although typical propagation delays are approximately 18 ns. The worst case delay corresponds to an effective throughput of one billion fuzzy logic inferences per second (one gigaFLIPS).