Light weight sector mapping scheme for NAND-based block devices

NAND-based block devices such as SD Card and USB Memory embed the special firmware called Flash Translation Layer (FTL) to emulate the block device interface. As the embedded FTL is executed by a low speed controller with a small sized SRAM inside the devices, its computation overhead and memory requirement should be low. However, the previous researches to improve the performance of FTL have mainly focused on reducing the number of the write and the erase operations of NAND flash memory with a low memory requirement. Reducing computation overhead has been overlooked relatively. In this paper, we present a light weight sector mapping scheme for FTL, which improves the performance of FTL with a low memory requirement and a low computation overhead. The key idea is to allow the log blocks, which are used as write buffer for the other NAND blocks, shared by multiple logical blocks and at the same time to prevent the sectors of a logical block from distributed to multiple log blocks in order to restrict the search space of a valid sector. A trace-driven simulation shows the presented scheme outperforms the existing sector mapping schemes in the most configurations. Especially in the skewed random write pattern, the improvement reaches more than 4 times as the number of log blocks increases.