Comparison of two architectures for implementation of the discrete cosine transform

A new DCT architecture developed by Mou and Jutand (1991) is compared to an architecture based on distributed arithmetic with ROMs realized as random logic. Both architectures have been implemented in 0.8 /spl mu/m CMOS technology and optimized with different constraints on area and timing. The results reveal that for HDTV applications the design with distributed arithmetic is superior, with lower power consumption and less than half the chip area.