A Compact Space and Efficient Drain Current Design for Multipillar Vertical MOSFETs

In the vertical MOSFET, due to its device structure, the bottom of its silicon pillar has a certain resistance because there is a diffused silicon wiring area in the bottom. Thereby, this resistance becomes large in the case of the multipillar transistors and also shows asymmetric characteristics between the top and bottom nodes of the pillar. This paper is devoted to examining this resistance for the multipillar vertical MOSFETs and proposing a compact design, which can suppress the resistance influences, attain a large drain current, and achieve a higher circuit performance.