Low cost wafer-level packaging method based on anodized aluminum substrate with backside signal pad and EMC passivation

As the need for compact and cost efficient package topology emerges, wafer-level package technology is favored by the industries[6]. To meet the industrial needs, our study was focused on wafer-level package method based on selectively anodized aluminum. By selectively anodizing the aluminum, the circuital port and local ground area is vertically connected to the bottom aluminum. The thickness of the selectively anodized aluminum layer is 80 μm and the thickness of the bottom aluminum layer is 40 μm. Simple microstrip line is fabricated on the anodized aluminum layer and EMC(epoxy molding compound) is molded on the whole wafer. For the bottom aluminum, the ports and the ground area is separated by chemical wet-etching technique. The wafer is diced by each unit cell, where we obtain our final packaged structure. The wafer-level package of this study provides minimum footprint and the fabrication process is quite straightforward. Also, an electrical model for the package structure, including the motherboard is presented. The electrical model may guide the future designers in optimizing the total package performance.