Indium deposition processes for ultra fine pitch 3D interconnections

With the miniaturization and the new capabilities in CMOS process, the interconnection pitch between a die and its circuits must be reduced as well. Therefore not only must the assembly steps adjust to the criterion associated with smaller pitches but the back-end wafer processing as well. In this paper we present two fabrication processes for the bumping of 8” wafers with pitches as low as 15μm. Indium was used as the solder and an electroplated deposition method as well as an evaporation method were developed. The two were qualified in term of bump height uniformity, process easiness, and were finally compared. A uniformity below 2% was obtained for the evaporation method and assemblies of large pixels array at a 15μm pitches achieved 99.9% to 100% connections. For the electroplating process uniformity of about 2-3% on the die and 7% on the wafer was achieved but no assemblies were performed.