Multi-VT engineering in highly scaled CMOS bulk and FinFET devices through Ion Implantation into the metal gate stack featuring a 1.0nm EOT high-K oxide

We demonstrate multi-V
_T
engineering on both CMOS bulk and FinFET devices through As implantation into a 1.0nm EOT TiN/high-K gate stack within a single metal single dielectric approach. We determine a As implantation process window enabling V
_T
tuning without any device degradation. It is shown that this approach is suitable for multi-V
_T
engineering with aggressively scaled dielectrics and, particularly, for fully depleted 3D device architectures.