Design implementation on FPGA of H.264/AVC intra decision frame

In this paper, we propose a hardware implementation of H.264 intra frame encoder to achieve the real-time operation for video conference applications. The H.264 intra frame encoder is composed by intra 4×4 prediction, intra 16×16 prediction, integer transform, quantization (AC & DC), inverse integer transform, inverse quantization (AC &DC), hadamard, and inverse hadamard transform. This method can process one macroblock in 573 cycles for all cases of macroblock type. The proposed hardware is implemented in VHDL. The VHDL RTL code works at 100 MHz in an Altera Stratix II FPGA. The execution time is decreased by 30%. The system also includes software running on an NIOS-II processor for implementing the pre-processing and the post-processing function. The H.264 intra frame encoder hardware and software are demonstrated to work together on ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA.