Characterization and modeling of RF substrate coupling effects due to vertical interconnects in 3D integrated circuit stacking

This paper discusses substrate coupling effects in 3D integrated circuits carried by TSV interconnects (Through Silicon Vias). These electrical couplings lead to several impacts on 3D circuit performance. RF (Radio Frequency) characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling and make obvious this phenomenon. New modeling tools for predictive studies have been validated thanks to a good compatibility between RF measurements and RF models.