A Unified Method for Calculating Capacitive and Resistive Coupling Exploiting Geometry Constraints on Lightly and Heavily Doped CMOS Processes

A method for calculating capacitive and resistive coupling is developed in this work, and its implementation in commonly encountered practical cases is presented. The method is based on the geometry of the coupling mechanism, and the derived model is therefore, in general, scalable and technology independent. The constraints of any related problem can easily be incorporated into this method, whereas pure 3-D effects, such as capacitive coupling, are fast and accurately computed. The proposed method is validated using measurements from a test chip in the UMC 0.18- μm CMOS lightly doped process, simulation data obtained by two commercial simulators, and theoretical results. The accuracy of the method is shown to be within 2%-10%.