A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS

This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We successfully confirmed the operation of the proposed CDR architecture at 5 Gb/s. The receiver is implemented in 65 nm CMOS, occupies 0.51 mm
²
, and consumes 178.4 mW at 5 Gb/s.