Power efficient distributed low-noise amplifier in 90 nm CMOS

A low-power wideband distributed low-noise amplifier (DLNA) in 90 nm CMOS is presented. Various techniques have been combined in the design to increase the distributed amplifier's power efficiency. These techniques range from moderate inversion biasing to transmission line tapering. The measured gain of the 12.5 mW DLNA is larger than 15 dB from DC to 21 GHz. The average noise figure in the pass-band is 5.4 dB, the IIP3 at 5 GHz is -6.6 dBm and the total die area is 0.41 mm
²
.