Register size vs. fault coverage in modified circular built-in self-test

Improvement in the effectiveness of circular built-in self-test (BIST) in practical applications is achieved by adding a shift register in the BIST chain with additional logic for deterministic pattern generation. The designer can increase the size of this additional register called the target register, to increase the cycle length of the state transition graph of the circuit in the BIST mode of operation for increased fault coverage. Design guidelines are given to assist in determining which circuits will be good candidates for this BIST approach.