Fixed-phase retiming for low power design

In this paper we introduce fixed-phase retiming, an optimization technique for reducing the power dissipation of digital circuits without sacrificing their performance. In fixed-phase retiming, we first transform any given edge-triggered circuit into a two-phase level-clocked circuit by replacing each flip-flop by two level-sensitive latches. Subsequently, while keeping the latches clocked on one of the phases fixed, we relocate the remaining latches onto interconnections with high glitching activity and capacitive load. We formulate fixed-phase retiming as a Boolean monotonic linear program and give an O(V/sup 6/ log V)-time algorithm for solving it, where V is the number of combinational blocks in the circuit.