Energy delay analysis of partial product reduction methods for parallel multiplier implementation

This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is currently the most popular choice for partial product reduction in parallel multipliers although 4:2 compressors can also produce equivalent results. Our energy delay analysis of these two schemes taking into account the architectural as well as circuit implementation issues suggests the superiority of the 4:2 compressor based partial product reduction technique as far as circuit delays, power consumption and architectural regularity are concerned. SPICE simulations of partial product generation using these schemes for an 8 bit multiplier suggest a worst case energy delay advantage of the order of 36% and 15% respectively for the 4:2 compressor based scheme in comparison with two different implementations of MBA. The corresponding figures for power reduction are of the order of 26% and 11% respectively.