An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits

In this paper the effects of technology scaling on the fraction of active power P/sub a/ wasted as short-circuit power P/sub s/ are studied through SPICE simulations. The accuracy of SPICE is verified against experimental data. SPICE simulations show that lowering V/sub T/ below 0.1 V can increase P/sub s//P/sub a/ significantly beyond what is expected from increased subthreshold leakage. P/sub s//P/sub a/ is typically higher at higher V/sub cc/ but to first order P/sub s//P/sub a/ is determined by signal slew rates and V/sub T/. It is shown that the input slew rate is constrained by P/sub s//P/sub a/ at low V/sub T/ and by performance at higher V/sub T/. We show that P/sub s/ increases with increasing gate sheet resistance. A simple analytical model for this effect is verified against the experimental data and used to determine the gate sheet requirements to maintain Ps/Pa<10% for sub-0.25 /spl mu/m technologies.