Modeling memory resources distribution on multicore processors using games on cellular automata lattices

Nowadays, there is an increasingly recognized need for more computing power, which has led to multicore processors. However, this evolution is still restrained by the poor efficiency of memory chips. As a possible solution to the problem, this paper examines a model of re-distributing the memory resources assigned to the processor, especially the on-chip memory, in order to achieve higher performance. The proposed model uses the basic concepts of game theory applied to cellular automata lattices and the iterated spatial prisoner's dilemma game. A simulation was established in order to evaluate the performance of this model under different circumstances. Moreover, a corresponding FPGA logic circuit was designed as a part of an embedded, real-time co-circuit, aiming at memory resources fair distribution. The proposed FPGA implementation proved advantageous in terms of low-cost, high-speed, compactness and portability features. Finally, a significant improvement on the performance of the memory resources was ascertained from simulation results.