PLL-based Clock Generator for Double-Sampled SC Filters with sampling rate up to 160 MHz

This paper describes a clock generator for a double-sampled SC filtering system. The circuit is based on a fast charge-pump PLL system that multiplies by a factor of 8 an external reference clock signal and ensures also a high precision and stability of the output clock phase. The maximum sampling rate of 160MHz is guaranteed by two 80MHz non-overlapped clock signals. The PLL is a third-order system with a bandwidth of 100kHz and a lock-in time of 15μs. The clock jitter is 500ps peak-to-peak. The total power consumption is 90mW at the maximum frequency rate and the total chip area is about 1mm
²
.