Development and Use of Flexible Block Libraries

The growing market of application-specific integrated circuits (ASIC's) implies the use of new design methodologies, in which the "fast design" and "error free design" aspects are considered to be at least as important as the chip area, power consumption and timing characteristics. These new methods are based mainly on the use of function-specific silicon compilers, or generators, able to produce the layout and net-list descriptions of a block, from a few given input parameters. These generators enable the skilled circuit-designer to save time when designing standard blocks such as RAMs or ROMs, and also enable the system-engineer to successfully carry out the design of other blocks such as bit-slice data-paths or random-logic blocks. The LOF system [1] has been used at the CNET over the last two years in order to build libraries of such generators. This paper presents the corresponding results.