A Systolic Processor for a Digital Video Matrix Operator

The proposed VLSI circuit performs the reverse matrix transformation of the luminance and color difference eight bit coded video signals into RGB signals. The chip is composed of 3 processors each one performing the linear function XA+YB+ZC. Each processor is a systolic array based on the Baugh-Wooley two's complement parallel multiplication algorithm. The chip has been design in order to support a 18 MHz maximum clock frequency in a 3.15 micron NMOS technology, it achieves a performance figure of merit of 9.5 10 T.Hz.mm-2.