A 2 μm CMOS, 10 MHz Microprogrammable Signal Processor Core with On-Chip Multiport Memory Bank

In this paper a 2 micron CMOS, MICROPROGRAMMABLE SIGNAL PROCESSOR CORE (SPC) is described, intended as the number crunching unit in Harvard-type digital signal processors. It contains a 16×16 bit Booth multiplier, a 40-bit accumulator, a 32 bit extractor, a format-adjuster, and a 3-port registerfile. Its projected 100 ns. throughput rate makes it highly suitable for applications like HiFi Audio, Telecom and Speech.