BGA lifetime prediction in JEDEC drop tests accounting for copper trace routing effects

Experimental drop test results of 2
^nd
-level assemblies can be influenced by numerous impact factors. The explicit definition of drop testing conditions by the JEDEC standard JESD22-B111 was intended to create a highly repeatable, and thus comparable, experimental setup. Recent developments showed, however, shifting failure modes from component to PCB side. Comprehensive drop tests were executed with 3 different memory packages. Failure analysis surprisingly found electrical fails of the assemblies on PCB side with broken copper traces next to the PCB pads. Detailed investigations showed a strong influence of the copper trace routing on their failure probability. Broken copper traces were only found when their routing direction was aligned to the dominating PCB deflection. The new experimental insights were proven by a two steps simulation approach. In the first step, an experimentally calibrated and validated 3-D JEDEC board model has been set up. In the second step, the copper trace routing effect was investigated by a 3-D sub-model of a single BGA component. The direction of copper trace routing showed a clear effect on the plastic copper strain. Simulation results were able to prove the experimental observations. Using these results, reliability modeling was started for two drop test configurations: 4-screw and 6-screw board clamping. In both cases, the sequence of failure of the components on the board was matched by using a combined criterion of plastic strain-rate and resultant force integral. The lifetime model based on this criterion was able to predict the experimental cycles-to-failure with less than 25% deviation.