An 81-MHz IF receiver in CMOS

An 81-MHz CMOS IF receiver for digital wireless applications is presented. The receiver consists of a continuous-time IF amplifier, a subsampling switched-capacitor gain stage, and a sixth-order bandpass /spl Sigma//spl Delta/ A/D converter. Incorporating 24 dB of programmable gain, the receiver achieves 92 dB of dynamic range in a 200 kHz bandwidth. Due to its IF sampling nature, the reciever is immune to de offset, flicker noise, and errors due to mismatches between I and Q signal paths. By utilizing a pseudo two-path resonator architecture in the bandpass /spl Sigma//spl Delta/ A/D converter, a stable passband center frequency which is immune to capacitor mismatch is achieved. Implemented in 0.8-/spl mu/m CMOS, this chip uses a single 3 V supply and consumes 14.4 mW of power.