A Low-Voltage Fourth-Order Cascade Delta–Sigma Modulator in 0.18-$\mu\hbox{m}$ CMOS

In this paper, a low-voltage fourth-order 2-2 cascade delta–sigma
$(\Delta\Sigma)$
modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented. In the analog part of the
$\Delta\Sigma$
modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order
$\Delta\Sigma$
modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented
$\Delta\Sigma$
modulator is fabricated in a 0.18-
$\mu\hbox{m}$
1P6M CMOS technology. The chip core area without PADs is 1.57
$\hbox{mm}^{2}$
. The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance.