Layout driven selecting and chaining of partial scan flip-flops

In an era of sub-micron technology, routing is becoming a dominant factor in area, timing, and power consumption. In this paper, we study the problem of selecting and chaining of scan flip-flops with the objective of achieving minimum routing area overhead. Most of previous work on partial scan has put emphasis on selecting as few scan flip-flops as possible to break all cycles in S-graph. However, the flip-flops that break more cycles are often the ones that have more fanins and fanouts. The area adjacent to these nodes is often congestive in layout. Such selections will cause layout congestion and increase in number of tracks to chain the scan flip-flops. We propose a matching-based algorithm to perform simultaneously the selecting and chaining of scan flip-flop taking layout information into account. Experimental results show that our approach outperforms the traditional one in final layout area.