All Digital Multiplying DLL Using Precision Digital Delay Line as DCO

In this paper all digital multiplying delay-locked loop (MDLL) is presented, which uses a 3rd order precision digital delay line (HDL) as DCO. Maximum locking frequency at 1.3V was 1GHz with multiplication factor of 50, assuming 20MHz reference clock frequency, and peak to peak jitter was  20ps. DCO consumed only 2.2mW, and the rest logic 3.5mW.