Discrete Test Structure Device Degradation Analysis and Correlation to NAND Flash Circuit Operation

A methodology is established to correlate shifts of test structure device parameters, due to device degradation or process variation, to circuit operation throughout the product lifetime. To the authors' knowledge, this work is original in that SPICE simulation is used, with degraded device models, to relate a circuit timing metric to the degradation of a discrete device used in the circuit. The correlation is validated with actual circuit measurements. In this study, the NAND Flash high-voltage switch circuit is examined in regards to the effect of degrading the p-channel MOSFET used in the circuit. Under standard operating conditions, the device degrades under high electric fields applied across the gate oxide. The method enables the accurate prediction of product lifetime using test structure measurements.