Low-cost flip-chip on board

For hand-held communication products, like the DECT telephone system, flip-chip on board offers minimization of both the package size and the occupied area on the boards. As a result of the reduction in interconnection lengths, the self-inductance is reduced. For high volume production, the compatibility of the flip-chip mounting technique with standard surface mount technology (SMT) reflow is essential. During reflow, the eutectic PbSn bump wets along the copper track, so the stand-off between integrated circuits (IC's) and the board is accurately defined by the layout of the board and the dimensions of the bump. The eutectic PbSn flip-chip processing is evaluated by impedance and cross-talk measurements, and in several reliability tests. For the electrical measurements, a zero-IF front-end IC is used. Wide-band measurements of the input impedance showed that the residual parasitics associated with the eutectic PbSn bumps are negligible compared with the parameters of the internal IC components. To accommodate the residual stresses from differences in coefficient of thermal expansion (CTE), the gap between the IC and the substrate is underfilled. This underfill material marginally affects the electrical behavior of the IC at frequencies up to a few GHz. As expected, a slight increase in the residual capacitance is observed. The effect of the underfill is studied by both temperature cycle and shock tests; cumulative failure distributions have been plotted. Results show that the adhesion properties and flow characteristics of the underfill material are the dominating factors for the number of cycles to failure. By selecting the proper underfill and curing conditions, the eutectic PbSn flip-chip construction can meet the test requirements for consumer communication products.