An Investigation for Leakage Reduction of Dual Transmission Gate Adiabatic Logic Circuits with Power-Gating Schemes in Scaled CMOS Processes

With rapid technology scaling, the proportion of the static power catches up with dynamic power gradually. To decrease leakage power is becoming more and more important in low-power design. This paper investigates leakage reduction of adiabatic circuits using power-gating schemes under deep submicron process. The energy dissipations of DTGAL (dual transmission gate adiabatic logic) circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. All circuits are verified using HSPICE, and BSIM4 model is adopted to reflect the characteristics of the leakage current. HSPICE simulations show that the leakage loss is greatly reduced by using the DTGAL power-gate techniques.