Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits

In this paper, a new very fast fault simulation method for extended class of faults is proposed. The method is based on a two-phase procedure. In the first phase, a novel parallel exact critical path fault tracing is used to determine all the "active" nodes with detectable stuck-at faults. In the second phase of the procedure, reasoning is carried out to determine the detectable physical defects based on the information about the "active" nodes and the current (or previous) logic state of the network.