Interconnects Integration for 0.25μm CMOS Technology

This paper presents the complete integration of a triple level metallisation (TLM) interconnection processes for a 0.25μm CMOS technology on 200 mm wafers. Advanced processes such High Density Plasma (HDP) deposition for phosphorus doped premetal oxide and for undoped silicon glass as inter metal dielectric (IMD), DUV lithography for all levels, collimated TiN barrier deposition, HDP etching of contacts and vias are used. This TLM interconnection scheme was implemented on 0.5μm CMOS base wafers provided by Centre Commun CNET-SGS Thomson Crolles. The electrical results are reported in terms of defectivity and intrinsic performances.