Advanced Ti Salicide Process for Sub-0.2 μm CMOS

Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of direct selective TiSi2 CVD deposition on gate and S/D. We show that these techniques provide solutions for silicidation of sub-0.2 μm CMOS devices.