A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O

A dual-PLL system for 45 nm SOI-CMOS processors is designed to clock a multi-protocol wireline I/O for high-speed digital communications covering a frequency range from 1 GHz up to 11.1 GHz. The two PLLs, based on a ring and LC-tank VCO, achieve .99 ps and 0.55 ps rms jitter, respectively. Circuit and architectural techniques to minimize the impact of SOI floating-body effect on phase jitter are introduced.