A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration

We present a 16b 250MS/S ADC that employs background calibration of the residue amplifier gain errors. It has an integrated input buffer and is fabricated on a 0.18¿m BiCMOS process. Without the input buffer, the SNR is 77.5dB and the SFDR is 90dB. With the input buffer, the SNR is 76dB and the SFDR is 95dB. The clock jitter is 60fs. The ADC consumes 850mW and the input buffer consumes 150mW.