A 390Mb/s 3.57mm2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS

Recent popularity of smart phones, netbooks, and other mobile broadband devices has vindicated 3G (WCDMA/HSPA) as an enabling technology for mainstream high-speed data and has given fresh impetus to its 4G successor, LTE (Long-Term Evolution). With mass deployment anticipated in 2-to-3 years, development of cost-effective and low-power LTE user equipment is currently keeping the wireless industry preoccupied. While the 1st-generation terminals will target 100Mb/s in the downlink, the MIMO-based LTE standard is capable of 326.4Mb/s [1] operation, which is more than 20× that of HSDPA. As with HSDPA, turbo decoding will be among the challenges (along with MIMO detection) in computation intensity, now threatening to be 20× higher. This contribution explores the feasibility of achieving the LTE maximum throughput with a turbo decoder ASIC realization, and the 100Mb/s milestone with competitive power consumption and die area.