Compact Layout of On-Chip Transformer

This study develops a compact layout for an on-chip transformer with both wide range of turn ratios and a high coupling coefficient in a small chip area. Analytical formulas are applied to calculate the self-inductances in the design stage. Therefore, six devices with various turn ratios are designed to verify the proposed layout. All devices are fabricated using foundry 130 nm complementary metal-oxide semiconductor technology. Measurements reveal that the proposed transformer has a wide range of
n
values (1-5.68) and high coupling
k
values (0.99-0.48) for a chip area of 100
²
¿m
²
.