Petri nets and asynchronous circuit design

Can a logic designer build a complex yet efficient asynchronous system completely or almost completely using formal methods and design tools? Is it possible to take a behavioural specification of the system and convert it into logic? What tools are needed and what tools are already available for this purpose? This presentation attempts to answer these and related questions by reviewing recent progress in development of methods and software tools based on Petri nets. Petri nets provide a rare combination of features that are essential in asynchronous circuit design: (i) a simple and easy to understand and manipulate graphical capture; (ii) modelling power that can be adjusted to various types of asynchronous behaviour at different levels of abstraction; (iii) formal operational semantics and verification of various correctness properties of both safety and progress types; (iv) possibility of synthesis of a circuit from its net model.