Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies

The evolution of the active area/isolation transition has resulted in modification of the isolation induced parasitic effects on the device. Based on experimental and simulation results, this paper presents an analysis of the corner parasitic effects induced by an abrupt transition. The substrate bias, transistor length and width dependence of the corner effect Is studied. It is shown that the corner parasitic transistor is less sensitive to short channel and substrate bias effects. The parasitic effect behavior as a function of certain technological parameters is studied by simulating the isolation process. It is demonstrated that certain technological parameters linked to the isolation process must be perfectly controlled for a good integration of future isolation technologies, especially for shallow trench isolation (STI).