A 1-V 1-Mb SRAM for portable equipment

Low-power and high-speed circuit techniques are described for 1-V battery operated SRAMs. A design concept is shown that uses two kinds of MOSFETs different in threshold voltages to reduce power dissipation due to the subthreshold leakage current in both standby and active modes. We propose a step-down boosted word-line scheme to reduce power dissipation in the memory array to 57% while accelerating the sensing speed. A novel bidirectional differential internal-bus architecture provides data transmission that is 45% faster than in the conventional architecture, yet without area or power penalty. A charge-recycling I/O buffer incorporating a data transition detector reduces the power dissipation of the I/O buffer by 30%. A 1-Mb SRAM designed using these techniques and 0.5-/spl mu/m CMOS technology demonstrated 4.8-mW power dissipation and a 75-ns address access time with standby power of 1.2-/spl mu/W at a 1-V power supply.